Micron® MTC21-P4 Controller Sub Chip Security Subsystem

Certificate

Approved Algorithms (27)

Security Levels (Table 1)

Derived Review-Risk Graph (review prompts, not findings)

flowchart LR
  %% Deterministic review-risk graph for Micron® MTC21-P4 Controller Sub Chip Security Subsystem
  %% Review prompts and evidence gaps, NOT vulnerability findings.
  subgraph CMVP["CMVP-disclosed clues"]
    C1["[high] Firmware / bootloader<br/>versions disclosed<br/>(identity, not provenance)<br/><i>Bootloader v1.0 [a], v1.1 [b, c], v1.0a [d]<br/>Boot ROM v1.0</i>"]
    C2["[high] Firmware update / recovery<br/>/ rollback services<br/><i>NVMe Update Key<br/>TCG Update Key<br/>ES2</i>"]
    C3["[high] Unauthenticated /<br/>self-test / status service<br/>surface<br/><i>Self-Test<br/>ES3</i>"]
    C4["[high] Physical/logical<br/>interfaces (some 'blocked<br/>in firmware')<br/><i>External Interrupt (JTAG, AHB bypass and inter-CPU…<br/>JTAG / AHB-32 bypass<br/>UART</i>"]
    C6["[low] Operating system / runtime<br/>referenced (boundary<br/>membership not asserted)<br/><i>bootloader<br/>application</i>"]
  end
  subgraph Inference["Derived inference"]
    I1["Component identity is<br/>disclosed, but provenance<br/>and patch lineage are not."]
    I2["Trusted code is reachable<br/>through update and<br/>recovery paths."]
    I3["Some services may process<br/>input before, or without,<br/>operator authentication."]
    I4["Interface reachability may<br/>vary by boot stage and<br/>lifecycle state."]
    I6["Possible only, a<br/>runtime/OS is referenced,<br/>but its membership in the<br/>cryptographic boundary is<br/>not established."]
  end
  subgraph Risk["Reviewer question"]
    R1["Do the vendor version<br/>strings obscure the<br/>upstream baseline, fork<br/>lineage, or known-CVE<br/>exposure?"]
    R2["Are update images<br/>authenticated before<br/>parsing, and are<br/>downgrade/rollback paths<br/>constrained?"]
    R3["Can unauthenticated<br/>services leak state,<br/>consume resources, or<br/>transition security state?"]
    R4["Are interfaces blocked<br/>before the bootloader<br/>runs, or only after<br/>approved mode starts?"]
    R6["If the OS/runtime is<br/>in-boundary, could its<br/>CVEs be hidden by<br/>firmware-only versioning?"]
  end
  subgraph Evidence["Evidence needed to close"]
    E1["SBOM / component baselines<br/>· patch and backport<br/>manifest · CVE disposition"]
    E2["update image format ·<br/>signature-before-parse<br/>proof · anti-rollback /<br/>downgrade policy"]
    E3["pre-auth reachability<br/>matrix · rate limits and<br/>output redaction ·<br/>abuse-case tests"]
    E4["lifecycle reachability<br/>matrix · boot-stage<br/>interface timing ·<br/>factory/recovery/error-state<br/>access controls"]
    E6["confirm the disclosure<br/>itself (keyword hit,<br/>context unverified) ·<br/>runtime identity and<br/>config · kernel/runtime<br/>hardening profile ·<br/>patch/backport manifest"]
  end
  C1 --> I1 --> R1 --> E1
  C2 --> I2 --> R2 --> E2
  C3 --> I3 --> R3 --> E3
  C4 --> I4 --> R4 --> E4
  C6 --> I6 --> R6 --> E6
  classDef clue fill:#eef3f9,stroke:#6f7f91,color:#1f3a5f;
  classDef infer fill:#fff7e6,stroke:#b98500,color:#6b4e00;
  classDef risk fill:#fbe9e9,stroke:#b02a2a,color:#7a1f1f;
  classDef evidence fill:#e6f4ea,stroke:#1e7d34,color:#14532d;
  class C1,C2,C3,C4,C6 clue;
  class I1,I2,I3,I4,I6 infer;
  class R1,R2,R3,R4,R6 risk;
  class E1,E2,E3,E4,E6 evidence;

flowchart LR
  %% Deterministic clue tier for Micron® MTC21-P4 Controller Sub Chip Security Subsystem
  %% confidence: high = structured record field; medium = structured but soft; low (dashed) = bare keyword hit, context unverified
  subgraph CMVP["CMVP-disclosed clues (deterministic)"]
    C1["[high] Firmware / bootloader versions disclosed (identity, not provenance)<br/><i>Bootloader v1.0 [a], v1.1 [b, c], v1.0a [d]<br/>Boot ROM v1.0</i><br/>src: certificate.firmwareVersions"]
    C2["[high] Firmware update / recovery / rollback services<br/><i>NVMe Update Key<br/>TCG Update Key<br/>ES2</i><br/>src: securityPolicy.services"]
    C3["[high] Unauthenticated / self-test / status service surface<br/><i>Self-Test<br/>ES3</i><br/>src: securityPolicy.services"]
    C4["[high] Physical/logical interfaces (some 'blocked in firmware')<br/><i>External Interrupt (JTAG, AHB bypass and inter-CPU…<br/>JTAG / AHB-32 bypass<br/>UART</i><br/>src: securityPolicy.portsAndInterfaces"]
    C6["[low] Operating system / runtime referenced (boundary membership not asserted)<br/><i>bootloader<br/>application</i><br/>src: text:keyword"]
  end
  classDef clueHigh fill:#eef3f9,stroke:#2f6fb0,stroke-width:2px,color:#1f3a5f;
  classDef clueMedium fill:#eef3f9,stroke:#6f7f91,color:#1f3a5f;
  classDef clueLow fill:#f7f7f7,stroke:#999,stroke-dasharray:4 4,color:#444;
  class C1,C2,C3,C4 clueHigh;
  class C6 clueLow;

Security Policy, page by page

Micron Technology, Inc. Micron Technology, Inc. Micron® MTC21-P4 Controller Sub Chip Security Subsystem Non-Proprietary FIPS 140-3 Security Policy Document Version: 1.6 Date: March 27, 2025 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. Table of Contents Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. List of Tables List of Figures Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. MTC21-P4 Controller Sub Chip Security Subsystem module, hereafter denoted the Module. The Module Guidance 2.3.B. Table 1

• Security Levels N/A N/A N/A Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. Cryptographic Module Specification The Module is a Single-Chip Hardware Sub-Chip cryptographic subsystem. The Module is intended for use by US Federal agencies or other markets that require FIPS 140-3 validated cryptographic controllers. The Module is a security subsystem within the ASIC Micron® MTC21-P4 SSD Controller package, whose intended use environment is within an SSD Controller. The Function ROM v3.0, Boot ROM v1.0 with Firmware Versions as indicated in Table 2 2.1 The cryptographic module is tested on the following: The Module versioning information is provided through the “Get Status” service and is returned as TCG Level 0 discovery content. The Module is Hardware and as such, Tested and Vendor Affirmed Operational Environments do not apply. Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. 2.2 Cryptographic Boundary The single-chip hardware, Micron® MTC21-P4 ASIC, is depicted in Figure 1 above, which also defines the physical boundary of the Module. The cryptographic boundary of the Module is defined by the Sub Chip Security Subsystem and includes all cryptographic algorithm implementations, as depicted by the red outline line in Figure 2 below. The TOEPP is defined as the area outside of the cryptographic boundary, but within the physical boundary of the single-chip on which the Module is installed. Micron® SSD Micron® MTC21-P4 ASIC NAND NAND NAND NAND NVMe TCv2.1 Module NAND NAND NAND NAND Sub Chip Security Subystem NAND NAND NAND NAND Single Chip Physical boundary Figure 2

• Module 2.3 Modes of Operation The Module only supports an Approved mode of operation and is configured to only operate in this Approved mode during manufacturing. To verify that the Module is in the Approved mode of operation, the operator may invoke the “Get Status” service, which will indicate the Approved mode of operation, as well as the version information for the Module. No initialization of the Module is required. The Module provides services through NVME industry standard commands as well as TCG commands. In addition, extra features are provided through the TCG commands. The Module provides these services to support the TCG mode of operation but is not responsible for TCG management functions. Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. 2.4 Security Functions The Module implements the Approved cryptographic functions listed in the table below. The numbers and letters within square brackets reference standards which are defined in the References and Definitions section of this Security Policy. Notes: The AES XTS algorithm implementation includes a check to ensure Key_1 ≠ Key_2; Key_1 and Key_2 are generated independently. AES XTS is only used for storage purposes per SP 800-38E Table 3

• Approved Algorithms Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. KTS-OAEPbasic PKCS1_v1.5 PKCS1_PSS Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. Table 4 – Vendor Affirmed Approved Algorithms The module does not support any non-Approved algorithms whatsoever. This includes algorithms that would otherwise be allowed in the Approved mode of operation, allowed in the Approved mode of operation with no security claimed, as well as not allowed in the Approved mode of operation. The module’s entropy was assessed before the ESV program was established and thus an entropy certificate is not applicable. 2.5 Security Function Implementation The following table shows the Security Function Implementations of the Module: Table 5 - Security Function Implementation (SFI) 2.6 Overall Security Design 1. 2. 3. 4.

5. The Module provides one distinct operator role: Controller, which acts as the Cryptographic Officer The Module provides role-based authentication. The Module clears previous authentications on reset. An operator does not have access to any cryptographic services prior to assuming an authorized role. The Module allows the operator to initiate power-up self-tests by power cycling or resetting the Module.
6. Power up self-tests do not require any operator action. Document Version 1.6 Micron Technology, Inc. Public Material – May be reproduced only in its original entirety (without revision).

Micron Technology, Inc.

7. Data outputs are inhibited during firmware loading, self-tests, zeroization, and error states.
8. Status information does not contain CSPs or sensitive data that if misused could lead to a compromise of the Module.
9. There are no restrictions on which keys or SSPs are zeroized by the zeroization service, except for the KManifestPUB_ROM.
10. The Module does not support concurrent operators.
11. The Module does not support a maintenance interface or role.
12. The Module does not support manual SSP establishment method.
13. The Module does not have any proprietary external input/output devices used for entry/output of data.
14. The Module does not output plaintext CSPs or intermediate key values.
15. The Module does not provide bypass services. 2.7 Rules of Operation The Module is embedded within the Micron® MTC21-P4 controller of the SSD. The Module shall be operated according to Section
16. Document Version 1.6 Micron Technology, Inc. Public Material – May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. Cryptographic Module Interfaces The Module’s ports and associated logical interface categories are listed in Table 6. Table 6

• Ports and Interfaces Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. Roles, Services and Authentication 4.1 Assumption of Roles and Related Services The Module supports one distinct operator role, the Controller (Cryptographic Officer). Table 6 lists the Controller (Cryptographic Officer) related services. In addition to the services listed in Table 6, the Module also supports a Self-Test service, which is invoked by power cycling the Module. All services are associated with the Controller (Cryptographic Officer) role with a sub-set of Controller services requiring an additional layer of authentication described in Table 7 below as “factoryrestricted”. These “factory-restricted” services require a second signature verification. The Module does not support a maintenance role or bypass capability. The Module does not support concurrent operators. *Requires additional authorization N/A N/A Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. 4.2 The role-based authentication methods are defined in Table 7 below. Table 8

• Roles and Authentication The RSA keys used for Controller authentication are loaded into the Module as part of a key manifest. The key manifest is itself verified by the Module using RSA signature verification with a key installed during manufacturing, KManifestPub_ROM. 4.3 All services implemented by the Module are listed in the Table 8 below. Each service description also describes the operator roles involved along with the interface command associated with the service. The SSPs modes of access shown in Table 8 are defined as:
• G = Generate: The Module generates or derives the SSP.
• R = Read: The SSP is read from the Module (e.g., the SSP is output).
• W = Write: The SSP is updated, imported, or written to the Module.
• E = Execute: The Module uses the SSP in performing a cryptographic operation. Implicitly include Read.
• Z = Zeroize: The Module zeroizes the SSP. The service indicator for approved services is the return code from an approved security service call (CCS). CCS = Command completion status and complies with the Approved Security Service Indicator defined in IG 2.4.C, Example Scenario #2. Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. Table 9

• Approved Services G,E PBKDF, AESKW G,E G G, E E G, E, Z G, E, Z W W G, E, Z E E E G, E, R G, E, R G, R E E E E E E W, E Z, G, R Z, G, R E E E W W E W, E E E E Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. W, R W, R W, R W, R W, R W, R W, R W, R W, R W, R E G, E, R G, E, R G, R E E Z, R E E E E, W Z, G, R E E E E G, E, Z G, W G, W E E E E; Z Z Z, G Z, G E R E R E, R G, E G, E E W Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. KAuthPub W W W W E E E E E E G, E G, E G, E G G G G, E G, E G G KDeviceIDPrivate KDeviceIDPublic G, R G, E G, R E G, E, Z G,E E The module does not support any non-Approved services, as it does not support a non-Approved mode of operation. The Module is composed of the following component(s):

• Security Subsystem Operational: Runtime SCSS firmware
• Security Subsystem Bootloader: Bootloader firmware
• Function ROM v3.0
• Boot ROM v1.0 Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. The Runtime SCSS firmware and Bootloader firmware are loadable components and are protected with the firmware load test using RSA signatures with a 3072-bit or 4096-bit key. This signature is also used to verify the integrity of the firmware prior to firmware execution. Firmware load and integrity checks are defined in the self-test section of this Security Policy. The ROM components are implemented in Non-Reconfigurable-Memory and are not subject to firmware integrity tests per FIPS 140-3 IG 5.A The operator can initiate the firmware integrity test on demand by power cycling/resetting the Module. Operational Environment The Module has a limited operational environment under the FIPS 140-3 definitions. The hardware tested configuration is listed in Table 2. The Module includes a firmware verification and load service to support necessary updates. Firmware versions validated through the FIPS 140-3 CMVP will be explicitly identified on a validation certificate. Any firmware not identified in this Security Policy does not constitute the Module defined by this Security Policy or covered by this validation. Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. The Module is a Single-Chip Hardware Sub-Chip cryptographic, and the embodiment is a production grade single chip. The chip is encapsulated in a standard IC package. The IC packaging itself provides the necessary opacity and tamper evidence required for Level 2 conformance. Table 10

• Physical Security Inspection Guidelines Figure 3
• Tamper Evidence Example The module does not support EFP/EFT mechanisms, as EFP/EFT are only applicable at Level 3 and the module only asserts Level 2 compliance. Hardness testing was not performed as it is only applicable at Level 3 and the module only asserts Level

Non-Invasive Security The Module does not implement any mitigation method against non-invasive attack. Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. Sensitive Security Parameter (SSP) Management The SSPs management methods as shown Table 10 are defined as:

• G1 = Externally generated using the DRBG during manufacturing
• G2 = Internally generated using the DRBG
• G3 = Derived using SP 800-108 compliant KBKDF
• G4 = Derived using SP 800-132 compliant PBKDF2
• G5 = Generated from an SP 800-90B compliant entropy source
• S1 = Only stored in dynamic, volatile memory (RAM) in plaintext
• S2 = Stored in static e-Fuse in plaintext
• S3 = Stored in static register in plaintext
• S4 = Stored in static ROM in plaintext
• E1 = Input in plaintext
• E2 = Input signed and verified using KManifestPub_ROM
• O1 = Output in plaintext public key
• O2 = Output using SP800-38F Key Transport (specify AES key wrap key)
• Z1 = Zeroized implicitly after use, by Module power cycle, and reset
• Z2 = Zeroized explicitly by the “zeroize” service by overwriting with a fixed pattern 9.1 Sensitive Security Parameters (SSP) All CSPs, PSPs, and non-SSPs used by the Module are described in this section. All usage of these SSPs by the Module is described in the services detailed in 4.3.. Table 11
• SSPs Function GeneratStrength N/A N/A N/A N/A N/A Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. SP800108 /

GeneratImport/Export N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision). K,

Micron Technology, Inc. GeneratImport/Export N/A N/A N/A N/A SumRdsKey (AESKW) K, TweakKey (AESXTS) 2.0 N/A WrapKey (AESKW) N/A N/A (FIPS1864) / N/A N/A (FIPS1864) / N/A N/A N/A KAuthPub Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision). K,

Micron Technology, Inc. Function GeneratStrength (FIPS1864) / KVSAuthPub N/A N/A N/A (FIPS1864) / N/A N/A (FIPS1864) / N/A SP800108 / N/A N/A N/A. for selftests N/A N/A N/A N/A KDeviceWrappingPub 150 KManifestPub_ROM for factoryrestricted RSAN/A (FIPS1864) / Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. 9.2 GeneratImport/Export N/A N/A N/A N/A The DRBG Randomness source (i.e., entropy) is using an internal ENT (P) source conformant to [90B]. Table 12

• Non-Deterministic Random Number Generation Specification

The Module performs self-tests to ensure the proper operation of the Module. Per FIPS 140-3 these are categorized as either pre-operational self-tests or conditional self-tests. Pre-operational and Conditional self-tests are both available on demand by resetting or power cycling the Module. All Conditional self-tests are performed before first use of the associated algorithm they are The self-tests error states and status indicator are described in Table 13 below: Table 13

• Error States Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. Boot ROM v1.0 are implemented in non-reconfigurable-memory and are not subject to the firmware Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

This section documents the operational behavior of the Module.

1. The Module clears previous authentications on power cycle.
2. Data output is inhibited during key generation, firmware loading, self-tests, zeroization, and error states.
3. Status information does not contain CSPs or sensitive data that if misused could lead to a compromise of the Module.
4. The Module zeroizes temporary values generated and used during self-tests.
5. The Module does not support a maintenance interface or role.
6. The Module does not support manual key entry.
7. The Module does not provide access to internal data structures.

The device is shipped from the factory in the Approved mode of operation. The keys generated during manufacturing are used to encrypt/decrypt data. On receipt of the Module, examine the product to ensure it has not been tampered with during shipping according to the procedures outlined in Section 7.

The Module does not implement any mitigation method against other attacks. Document Version 1.6 Micron Technology, Inc. Public Material

• May be reproduced only in its original entirety (without revision).

The following standards are referred to in this Security Policy. Table 16

• References Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).

Micron Technology, Inc. Table 17

• Acronyms and Definitions Document Version 1.6 Micron Technology, Inc. Public Material
• May be reproduced only in its original entirety (without revision).